Jedec publishes final specifications of DDR5 memory standard

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The Jedec organization has published the final specifications of the ddr5 memory standard. Among other things, DDR5 supports twice the bandwidth of DDR4. The new memory standard must also work more efficiently.

Jedec announced the publication on its website. These specifications were largely already known, but are now final. The publication of the standard should help chip manufacturers in the design of upcoming products and platforms, AMD reports, among others, in the announcement of Jedec.

The standards organization confirms on its website, among other things, that the memory density of DDR5 will be increased to 64Gbit per chip. With DDR4 memory this was 16Gbit. In time, this should ensure that individual dimms can hold up to four times more memory, although this will not be the case immediately upon release.

The bandwidth of DDR5 is expected to be 4.8Gbit / s upon release, Jedec reports. In the coming years this will be gradually increased to probably 6.4Gbit / s. The current bandwidth of ddr4 is 3.2Gbit / s, although it was about 1.8Gbit / s at release.

DDR5 modules offer higher bandwidth than DDR4, even at identical speeds

This increase is achieved, among other things, because a memory module is divided into two channels, Anandtech writes. Instead of a single 64-bit data channel, DDR5 offers two separate 40-bit channels per dimm. This concept is already used for memory types such as gddr6.

The burst length is in turn doubled to bl16, which allows both memory channels to handle 64 bytes per operation. This theoretically allows a DDR5 dimm to perform two 64 byte operations in the time it takes a DDR4 module to execute one, depending on the memory speed. This provides double the effective bandwidth. At the same time, the number of banks will be doubled to 32, which, according to Jedec, should also ensure better performance.

The ddr5 memory chips also receive error-correcting code on the memory chips themselves. It is not clear if this is standard for all ddr5 modules. The power consumption of DDR5 has also improved compared to its predecessor, Jedec reports. For example, the dimms get voltage regulators integrated, while this was previously controlled by the motherboard. This should simplify the production of motherboards somewhat. The integrated voltage regulators can also reduce power consumption and limit the influence of voltage fluctuations, making more dram chips usable and thus improving yields.

The power consumption must be further reduced because the vdd is reduced from 1.2V to 1.1V, as was already known. Ddr5, like its predecessor, uses 288 pins. However, the layout of these pins has changed, so the modules do not work in ddr4 slots.

It is not yet clear when the first ddr5 modules will hit the market, although it is expected to happen in 2021. Both Intel and AMD have not yet announced consumer platforms that can make use of the memory. Intel does have Sapphire Rapids on its roadmap. This server platform is due to be released in 2021 and offers support for ddr5 and pci-e 5.0. It is expected that ddr5 will first be introduced for the hpc and server market, and later also become available to consumers.

Earlier this year, Micron announced that the company has started distributing DDR5 samples to a limited number of data centers. The same company is now reporting that it is starting a DDR5 enablement program, which should speed up the introduction of DDR5. SK Hynix also previously published about its plans for DDR5. The company mentioned the arrival of DDR5-8400.

SK Hynix previously published about ddr5

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