IBM, GloFo and Samsung to use gate-all-around transistors for 5nm chip

IBM, Global Foundries and Samsung have a method ready to produce energy-efficient 5nm chips based on euv lithography. They do not use finfet transistors, but gate-all-around transistors.

With today’s 10nm chips, chip manufacturers use finfets: a fin between source and drain is enclosed by a gate on three sides and forms a double gate. Finfets can also be used for 5nm production, but IBM, Samsung and Global Foundries think they can make more efficient chips with gate-all-around or GAA transistors. With gaa, the gate is all the way around the nanowires of channels, and the larger area of ​​gates should allow for faster, smaller and more economical transistors. IBM can stack the nanolayers by using euuv lithography.

IBM claims that 5nm chips based on the technology perform 40 percent better or are 75 percent more economical with equal performance compared to comparable 10nm versions. The technology should enable chips the size of a fingernail with 30 billion transistors, IBM claims. It is not there yet, for the time being it is only a production technique on paper. The company will publish details about the method at the VLSI Technology and Circuits conference taking place this week in Japan, under the heading Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET.

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