European Arm CPU for supercomputers gets 72 cores, supports hbm2e and ddr5

The French SiPearl, which is developing a CPU for supercomputers with financial support from the European Processor Initiative, is working on an Arm CPU with 72 cores and support for hbm2e memory and ddr5. The chip can be made in 7nm or 6nm.

SiPearl itself has not yet given detailed information about its first processor, but on Twitter is an image which shows the design of the first cpu codenamed Rhea. The photo was taken during a tour of a politician at the company.

The photo shows that it is a processor with 72 cores. SiPearl announced in April that it had purchased a license from Arm for the use of the new Zeus core. That is the successor to the Neoverse N1 core, which is already used in server processors.

The image reveals that the chip will have four hbme2 memory controllers and four to six ddr5 controllers. According to AnandTech, this indicates a hybrid system in which the very fast hbm2e memory could be combined with larger quantities of ddr5 dimms.

Rhea processor design from SiPearl. Photo via Alexandra Dublanche on Twitter

The photo shows that the design is intended for production on TSMC’s 7nm process, while SiPearl has previously indicated on a roadmap that it will have its processor made at 6nm. However, TSMC’s 7nm and 6nm processes are design compatible, the design can therefore be made on both processes.

SiPearl wants to release its first processor in 2021 for high performance computing. A year later, a chip should follow that can be used in exascale supercomputers. The French company is working on the chip in collaboration with and with financial support from the European Processor Initiative. This initiative consists of 27 partners from 10 European countries.

Earlier this year, a Japanese supercomputer equipped with Fujitsu Arm CPUs and hbm2 memory took first place on the Top500 list of supercomputers. The Fujitsu chip features 48 cores with a custom design based on the Armv8.2-A instruction set.

Roadmap of SiPearl and European Processor Initiative

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