TSMC aims to start mass production of 3nm chips in 2022. They could then operate 25 to 30 percent more efficiently than the first generation 5nm chips with the same performance, or perform 10 to 15 percent better with the same consumption.
TSMC provided an update on its roadmap at its Worldwide Technology Symposium. The Taiwanese chipmaker is currently producing large quantities of 5nm chips and is working on an improved 5nm process it calls N5P. Mass production of these should start next year and chips based on that node can perform 5 percent better with the same consumption or 10 percent more efficient with the same performance.
In 2022, a re-improved 5nm chip process is due to be mass-produced and TSMC calls this N4. TSMC has not yet specified what improvements this node should bring to chips. Next year TSMC wants to make the first test chips at 3nm, followed by mass production at the end of 2022. This N3 node must therefore yield up to 30 percent more efficient chips or up to 15 percent better performing chips, with TSMC comparing with N5, the first 5nm generation. The differences compared to N5P or N4 are therefore smaller.
TSMC is going to make more chip layers with EUV machines for each node and at N4, for example, the company expects to need fewer masks, which will increase the costs for production. The company seems to be getting more and more under control of EUV production, as evidenced by the claim that the yield, the yield of functioning chips, is higher at N5 than at N7 and N10, with more improvements to be made. AnandTech explains that TSMC still uses finfet transistors in its 3nm production. Samsung previously announced that it will switch to gate all-around transistors for its 3nm node.
For internet-of-things chips, TSMC has developed a new, economical 12nm production line, in which the company now also uses finfet transistors. The company compares this N12e node with its 22nmultra-low leakage node, which the company also offers for IoT chips, and claims that N12e offers 49 percent higher performance with the same power consumption or 55 percent lower power consumption with the same performance. Among other things, TSMC would have reduced the leakage currents at SRAM by half.
|TSMC chip nodes|
|N5 (5nm) compared to N7 (7nm)||N5P (5nm) compared to N5 (5nm)||N4 (5nm) compared to N5 (5nm)||N3 (5nm) compared to N5 (5nm)|
|Consumption with equal performance||-30%||-10%||?||-25-30%|
|Performance with the same consumption||+ 15%||+ 5%||?||+ 10-15%|
|Risk / mass production||Mass production||2021||Risk at the end of 2021 / mass production 2022||Risk 2021 / mass production end of 2022|