Toshiba increases flash capacity with first qlc nand chips

Toshiba has increased the capacity of its flash memory by fifty percent by switching to qlc technology. This means that each memory cell can contain four bits, while this concerns three bits in the case of tlc-nand.

The latest qlc memory chips, short for quadruple-level cell, have a capacity of 768Gb per die and follow the tlc chips with 512Gb capacity per die. As with its tlc-nand, Toshiba says it can stack sixteen dies in a package, with which the capacity per chip is 1.5 TB, compared to 1 TB per chip of the tlc memory. Toshiba can store 768Gb, or 96GB, in its dies by using its latest generation bics memory, or 3d-nand with 64 layers.

To be able to store four bits per memory cell, the precision with which the charge in the cells can be read must be much higher than with mlc- or even tlc-nand. Electrons are stored in the floating gate of a memory cell and the amount of electrons indicates whether bits are read as 0 or 1. With more bits, the charge differences between the bits are smaller and the reading must therefore take place with greater precision. This is easy with slc memory, with mlc a bit more difficult and with tlc the differences are even smaller. Toshiba says it has enough precision for its qlc to be able to do that successfully.

The Japanese company does not say at what speed bits can be read and written. Because the charge differences become smaller with more bits per cell and more precision is needed to read and write the correct bit value, the reading and writing also take longer. Therefore, with more and more bits per cell, nand is slower and slower. Nevertheless, Toshiba says that its qlc-nand is suitable for server applications, but mainly as economical and more compact replacements for hard drives, without sacrificing much in capacity. Toshiba is currently supplying samples to SSD and controller manufacturers and will be demonstrating its nand chips at the Flash Memory Summit in early August.