Intel announces new AVX10 instruction set for both P and E cores
Intel will equip future processors with the new AVX10 instruction set architecture. In it, support for 512bit calculations becomes optional, which makes it possible to use the instruction set extension on both P and E cores.
Currently, AVX-512, so far the latest iteration of Intel’s expansion on the x86 architecture, by definition requires support for 512bit instructions. However, the low-powered E-cores that Intel uses in its processors today cannot execute such large instructions, and mixing cores that support and do not support different instructions is not possible in modern operating systems. That is why the processor manufacturer was forced to eliminate full AVX-512 hardware support on its twelfth and thirteenth generations of Core processors, even though the P-cores were designed for that. Conversely, Intel was therefore unable to use E-cores for its Xeon server processors, which do offer AVX-512 support.
In the new AVX10-isa, the ability to execute 512bit instructions with both integers and floating point numbers becomes optional and support for 256bit-embedded rounding is added. As a result, software that supports AVX10 can also run on E-cores, albeit less quickly. This paves the way to make this instruction set extension available on all future Intel processors, Intel writes a technical paper about the new isa.
The first processors that will support AVX10 will be the Xeon CPUs, so far known under the code name Granite Rapids. They will probably not come onto the market until late 2024 or early 2025. We probably shouldn’t expect consumer processors with AVX10 much before then. To maintain backward compatibility with existing chips, there will be two versions of AVX10: AVX10.1 and AVX10.2. Version 10.1 is the legacy version, version 10.2 adds support for E-cores. The idea is that AVX10 software supports both versions and automatically chooses the correct one based on the detected processor.
At the same time as AVX10, Intel announces the arrival of Advanced Performance Extensions, abbreviated APX. APX doubles the number of generic registers from 16 to 32, which means fewer loads and stores are needed to and from the L1 caches. That could make processors both faster and more economical in the future.