Western Digital and Kioxia Introduce 162 Layer Nand Memory

Western Digital and Kioxia, the former Toshiba Memory, have presented their sixth generation nand memory. The new generation uses 162 layers, which was 112 layers in the previous generation.

According to the memory manufacturers, who have been collaborating for 20 years, sixth-generation NAND memory chips are 40 percent smaller than previous-generation NAND chips at the same capacity. That’s because of the stacking of more layers and a ten percent increase in lateral density of the memory cells.

The manufacturers write in a press release that they apply a Circuit Under Array CMOS design, where driving logic is placed under the memory cells; that should reduce bit programming time. Micron and SK Hynix have been doing this for some time with their nand memory. According to WD and Kioxia, this improves performance and read latency. The manufacturers claim a 66 percent performance gain in I/O performance over the previous generation. The read latency would be reduced by ten percent.

Due to all the improvements, 70 percent more bits are produced per wafer compared to the previous generation, the memory makers say. The manufacturers do not state in their press release how many bits per cell the memory contains. The fifth generation nand memory was TLC nand with three bits per cell.

It is not yet known when SSDs with the new NAND memory will be released. The BiCS5 memory of the previous generation is included in the Kioxia Exceria M.2 SSDs. Those are relatively cheap NVMe SSDs.