Imec has made surrounding gate transistors based on vertically placed nanowires with good electrical properties. With the transistors, imec can manufacture the smallest SRAM cells to date.
The size of a 6T sram cell with the surrounding gate transistors would be between 0.0184 and 0.0205 square micrometers. The design is aimed at using a 5nm node, but has good properties regarding the distance between the vertical nanowires: it is 50nm.
The surrounding gate transistors are particularly suitable for sram, memory that, unlike dram, does not need to be refreshed and that is cached in CPUs. The size of the 6T sram cells is based on the area of the bit cells of static random-access memory, consisting of six transistors. SRAM is expensive and limited in scope, something that imec’s invention could improve upon in the future.
With the surrounding gate transistors, the gate is completely around the channel, allowing full control over the channel. The vertical instead of horizontal placement now reduces the size and surface area, putting lower fuel consumption and higher speeds within reach.
The new type of transistor is not suitable for processors, or logic. For processors, the semiconductor industry is looking for an alternative to finfets. The performance of finfets deteriorates with further reduction of the fins, due to the smaller contact surface between gate and channel. This is especially true at 3nm. However, replacing a single finfet while maintaining performance would require three surrounding gate transistors, again negating the surface gain here. Imec sees a greater future here in the use of alternative materials for finfets, nanosheets instead of nanowires and something the institute calls complementary fets.
Imec conducted the research with the Singaporean company Unisantis, which invented the surrounding gate transistors. The institute and the company announced the progress during the Imec Technology Forum, which will take place this week in Antwerp.