Software Update: Memtest86 10.0 build 1000

PassMark Software has released version 10.0 of Memtest86. This program allows the internal memory to be subjected to a rigorous test in order to reveal any problems. Memtest86 was developed in 1994 by Chris Bradly and in early 2000 the perhaps even more famous Memtest86+ was created as a fork, which often leads to confusion. Since 2013, it is owned by PassMark Software and is available in a free and paid format performance. Below is the changelog since version 9.1:

Version 10.0 (Build 1000)

New Features

• Added new experimental memory test as Test 14 [DMA test]. This test exercises the disk controller’s DMA hardware to perform memory access, bypassing the CPU. The motivation for this test came from discovering a defective RAM module that did not produce errors when accessed via the CPU, but failed when files were read from disk via DMA. As this test is experimental, it shall be disabled by default.
• DIMM (Pro edition)/chip-level (Site Edition) error detection on limited number of hardware platforms. This includes mid-test error reporting, graphical UI summary report on test completion and per-DIMM/chip error count table in the HTML report.
• Added new config file parameter, ‘CPUMAP’, to specify the DRAM chip labeling map. By default, DRAM chips are labeled consecutively starting from U0 (eg. U0, U1,…, U15)

Fixes/Enhancements

• Log file name now includes the timestamp
• Added new blacklist flag ‘DISABLE_CPUINFO’ for disabling CPU info collection
• Fixed ‘MAXCPUS’ config file parameter not being applied
• Fixed hammer test incorrectly running in single-sided mode in Free version
• Fixed clock speed measurement failure for ARM chipsets due to cycle count register not being enabled
• Fixed detection of MAC address used as unique ID for PXE boot
• Added support for reporting IBECC errors
• Fixed bug in reading ECC error count registers for various Intel/AMD Ryzen chipsets
• Fixed reading ECC error status register for Intel Tiger Lake-H and Alder Lake chipsets
• Fixed ECC detection on Intel Ice Lake-SP chipsets
• Added ECC detection support for multi-socket Intel Ice Lake-SP chipsets
• Fixed ECC support for Intel Rocket Lake chipset variant
• Added ECC support for AMD Ryzen Zen 3 50h-5fh chipset
• Fixed ECC support for AMD Ryzen Zen 2 chipsets with 2 memory channels
• Fixed ECC error false positives on Intel Atom C2000 chipsets
• Added support for retrieving Intel Ice Lake-SP CPU info
• Added support for retrieving Intel Ice Lake-SP RAM SPD data
• Added support for retrieving Intel Ice Lake-SP RAM temperature data
• Added SMBus (SPD) support for Intel Alder Lake-P
• Enable SMBus on Intel 801-based chipsets if disabled
• Fixed detection of SPD modules on systems with > 8 SMBus controllers (eg. quad socket systems)
• Fixed bug in mapping SPD module index to SMBIOS slot index
• Fixed detection of SPD slot for systems with soldered and removable DIMMs
• Fixed incorrect calculation of DDR5 transfer bandwidth
• Fixed DDR5 memory type in SMBIOS not being correctly parsed
• Fixed identification of data partition in USB flash drive
• Create ‘Benchmark’ directory to store RAM benchmark results if it does not already exist
• Updated black list

Version 9.4 (Build 1000)

Fixes/Enhancements

• Added new config file parameter, ‘MAXCPUS’, for setting the maximum number of CPU logical cores used for testing. By default, this value is 256 (Pro Edition) and 16 (Free Version). This parameter can be set to a maximum value of 512.
• Added new config file parameter, ‘AUTOPROMPTFAIL’, for specifying whether to display the test result and ask for user intervention on test failure, even when AUTOMODE is enabled
• Added new config file naming convention allowing for separate config files depending on memory size: GB-mt86.cfg
• Fixed memory size calculation to use rounding instead of truncation
• Display PASS message box in yellow (instead of green) on test completion if corrected ECC errors were detected
• Display error message if no valid SPD.spd file was found when SPDMATCH=1
• Display error message if no SPD modules were detected when SPDMATCH=1
• Display error message and exit MemTest86 when failing to measure CPU clock speed during startup
• Updated XML message to include CPU info & SMBIOS info sent to PXE server/management console
• Added ECC Support for Intel Tiger Lake H chipset
• Added ECC Support for Intel Rocket Lake chipset
• Added ECC Support for Intel Alder Lake chipset
• Added ECC Support for Intel Ice Lake-SP chipset
• Added support for retrieving CPU info for Intel Elkhart Lake chipset
• Added support for retrieving DIMM temperatures (TSOD) for Intel Alder Lake chipset
• Fixed issue with measuring ARM64 CPU clock speed due to CPU cycle counter (PMCCNTR) being disabled
• Fixed HTML report to display error bit map in text when copying/pasting
• Fixed Linux badram entries in HTML report to be page size aligned (4096 bytes)
• Fixed parsing bug with SPD.spd file when whitespace appears at the end of each line
• Fixed issues with displaying RAM SPD DDR5-specific info
• Fixed support for limited number of command line parameters in Free version
• Fixed bug in overflowing text in SPD info screen
• Fixed REPORTNUMWARN config file parameter not being written when saving config file
• Included Serva PXE server configuration file in Site Edition package
• Updated blacklist with Dell Precision 7760 screen display issues

Version 9.3 (Build 1000)

Fixes/Enhancements

• Support custom test definitions specified by a configuration file. A custom test definition consists of an existing test algorithm, specific test pattern, cache settings, and number of iterations. Custom test definitions are enabled by specifying the TESTCFGFILE parameter (Pro Edition only)
• Fixed incorrectly formatted XML Status/TestResult files sent to PXE/TFTP server (Site Edition only)
• Fixed incorrect reporting of error endianess for 128-bit test
• Fixed bug in displaying/logging ECC error channel/slot number
• Fixed report/log files not being saved correctly for non-standard USB flash drive installs
• Improved responsiveness of pattern string updated on screen
• Display row hammer warning, if applicable, in test completion popup message
• Fixed ECC error reporting on AMD Ryzen chipsets to include channel/slot information
• Fixed ECC error reporting on AMD Ryzen chipsets with 8 memory channels
• Improved robustness of ECC error reporting for Intel Atom C2000 chipsets
• Fixed retrieval of DDR4 SPD bytes on Intel Alder Lake chipsets
• Added support for parsing DDR3 Module Manufacturer’s Specific Data
• Updated blacklist with additional Surface Pro models with display issues

Version 9.2 (Build 2000)

Fixes/Enhancements

• Added large PASS/FAIL block text to top-right corner of HTML report
• Added visual representation of bit error mask to HTML report
• Fixed missing timestamp for ECC errors in HTML report
• Fixed incorrect version string indicating “V9.1” instead of “V9.2”