PCI-SIG shares draft version of PCIe 7.0 standard – update

Standards organization PCI-SIG has shared the first specifications for PCIe 7.0. The new version should offer bandwidths of up to 256GB/s with sixteen lanes, twice as much as PCIe 6.0. This first revision concerns a draft, which will be supplemented in the coming years.

PCI-SIG recently shared revision 0.3 of the PCIe 7.0 standard, writes Anandtech. That version serves as the first draft that is sent to PCI-SIG members. This allows the next phase of the PCIe 7.0 development process to begin. Revision 0.3 itself offers few concrete technical details, beyond what PCI-SIG previously reported about PCIe 7.0.

As with previous generations, the organization wants to double the bandwidth with PCIe 7.0 compared to its predecessor. The standards organization states in documents that the new version will have data rates of 128GT/s, among other things. A PCIe 7.0 connection should therefore provide bandwidths of up to 16GB/s per lane.

For x4 SSDs, the theoretical PCIe 7.0 bandwidth is 64GB/s, while for x16 video cards it is 256GB/s. With PCIe 6.0, the specifications of which were finalized last year, the maximum bandwidth is 8GB/s per lane. PCIe 5.0, with which the first products are now compatible, has a bandwidth of 4GB/s per lane.

The PCIe 7.0 standard must also use PAM4 signaling for data transmission. The PAM4 modulation uses four voltage levels to encode 2 bits of data. This leads to higher data transmission, but also makes the signal more fragile and is therefore accompanied by a higher bit error rate. Pam4 signaling is also already used in PCIe 6.0.

PCI-SIG finalized the PCIe 6.0 standard early last year and almost immediately started work on PCIe 7.0. The standard should be ready in 2025. PCIe 7.0 products will appear in subsequent years.

Update, 1:32 p.m: This article stated that PCIe 7.0 would offer speeds of up to 512GB/s, but it was supposed to be 256GB/s. The article has been adjusted accordingly.

Source: PCI-SIG, via Anandtech