AMD is working on 3d stacking dram and sram on processors

AMD is developing techniques for stacking dram and sram on processors with through-silicone via channels for the connections between the dies. The 3D stacking technique has to compensate for the fact that Moore’s Law has come to an end.

According to Tom’s Hardware, AMD is working on 3D stacking of processor layers, general manager Forrest Norrod announced during the Rice Oil and Gas HPC conference. Manufacturers are already stacking chip layers, but this involves package-on-package technology in which the upper memory layers are connected with standard BGA connections. This allows efficient use of space, but does not yield much speed gain.

According to Norrod, reducing chip structures no longer yields frequency improvements. “With the next node, if we don’t do special things, we get less frequency,” he says. Traditionally, switching to smaller production processes is associated with both lower consumption and higher clock speeds. However, this corollary of Moore’s Law is under pressure.

AMD therefore wants to connect stacked dies with through-silicon vias. These are microchannels for fast data connections between the layers. Intel is working on similar techniques that it presented last year under the name Foveros. Intel uses the techniques, among other things, to combine chip components made with different production processes, such as a 14nm I/O die with a 10nm core die. AMD is also working on making its processors modular. The company builds chiplets by connecting components to its CCIX-Gen-Z interconnects.