StarFive announces VisionFive V1 board with dual-core RISC-V soc for $150

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StarFive has unveiled a new VisionFive V1 singleboard computer. The board will include a dualcore RISC-V soc. It appears to be an updated version of the BeagleV SBC, which was announced early this year but never went into production.

The Chinese company StarFive will officially present the VisionFive V1 on December 8 during a RISC-V summit in San Francisco, writes German tech website Heise. Specifications and slides of the singleboard computer have already been published. This shows that the VisionFive V1 has a StarFive JH7100 soc, which has two SiFive U74 that run at 1.5GHz and are based on the RISC-V architecture. These cores should deliver approximately the performance of Arm Cortex-A55 cores.

Furthermore, the VisionFive V1 gets 8GB Lpddr4 memory and 2MB L2 cache. The single-board computer will also have a size of 100×72 mm and will have four USB 3.0 connections, a gpio header with 40 pins, a 3.5 mm jack and a MicroSD card reader. The SBC also gets an HDMI 1.4 connection, an RJ45 connector for Gigabit Ethernet and support for Wi-Fi 4 and Bluetooth 4.2. The VisionFive V1 is powered via USB-C.

It is not yet known when the VisionFive V1 will be released. StarFive may announce the release date during the RISC-V summit on December 8. The company’s slides do state that the single-board computer will cost $150. The company is also working on a V2 variant, which should include a RISC-V soc with four cores.

The VisionFive V1 has almost exactly the same features as the BeagleV, a singleboard computer that was developed by seeed and beagleboard.org and would receive a soc from StarFive. That SBC was announced in January this year, but never went into large-scale production and was scrapped entirely in July. StarFive already indicated at the time that the company is working on another RISC-V development board. This may be the VisionFive V1. Whether this SBC will eventually go into production remains to be seen.

Sources: StarFive website and slides RISC-V summit

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